1. Field of the Invention
The present invention relates to a semiconductor memory device and a method for manufacturing the same, and more particularly, relates to a semiconductor memory device including a capacitor film formed of an insulating metal oxide and a method for manufacturing the same.
2. Description of the Related Art
Along with an improvement of digital technology, the tendency to process and store a large capacity of data has been promoted, resulting in an increased sophistication of electronic apparatuses, and with regard to a semiconductor device used in these apparatuses, a significant reduction of the semiconductor element size has been sought.
In accordance with this trend, techniques of using a highly dielectric material for a insulating capacitor film, instead of conventional silicon oxides or nitrides, are being widely researched and developed in order to realize a higher integration of a dynamic RAM.
In addition, Researches and developments are actively under way on ferroelectric film having spontaneous polarization characteristics, in order to obtain a practical non-volatile RAM capable of a low voltage operation and a high reading/writing rate.
The most crucial objective for realization of such semiconductor memory devices is to develop a process capable of integrating a capacitor element on a CMOS integrated circuit without characteristic degradation.
Hereinafter, referring to FIG. 6, a conventional semiconductor memory device 500 and a method for manufacturing the same will be described.
As shown in FIG. 6, the semiconductor memory device 500 includes a semiconductor substrate 33 on which a transistor 34, including source and drain regions 21 and a gate electrode 22, is formed. A first protective insulation film 23 is formed to cover the entire surface of the semiconductor substrate 33.
A data storage capacitor element 35 is formed on the first protective insulation film 23. The capacitor element 35 includes a lower electrode 24, a capacitor film 25 formed of an insulating metal oxide, and an upper electrode 26.
A hydrogen barrier layer 27 having the function of an interconnection layer is formed to cover the data storage capacitor element 35. A second protective insulating film 28 is formed to cover the entire surface of the first protective insulation film 23 and the hydrogen barrier layer 27.
By etching the second protective insulating film 28 and the hydrogen barrier layer 27, contact holes 29 partially exposing the upper electrode 26 and a contact hole 30 partially exposing the lower electrode 24 are formed. By etching the first protective insulation film 23 and the second protective insulating film 28, contact holes 31 partially exposing the transistor 34 are formed. Finally, an interconnection layer 32 connecting the transistor 34 and the capacitor element 35 is formed in a predetermined location.
In the conventional semiconductor memory device 500, the hydrogen barrier layer 27 is formed to cover the capacitor element 35. Because the hydrogen barrier layer 27 is formed of a material acting as a barrier against hydrogen in the process after the interconnection layer 32 is formed, the hydrogen barrier layer 27 is capable of suppressing the characteristic degradation of the capacitor element 35 caused by the reduction reaction of the capacitor film 25 formed of an insulating metal oxide.
The inventors of the present invention have found, however, the conventional process mentioned above has yet another unsolved problem in the process prior to the formation of the interconnection layer 32. Now, this problem will be described referring to FIGS. 7A through 7D.
As shown in FIG. 7A, a resist layer 61 is formed on the second protective insulating film 28 for forming the contact hole 29 through the second protective insulating film 28 and the hydrogen barrier layer 27 formed on the upper electrode 26 formed of platinum.
As shown in FIG. 7B, the resist layer 61 is then removed using an oxygen plasma. In this process, a part of the OH bases 62 generated during the removal of the resist layer 61 are decomposed by the catalytic reaction on a surface 26A of the upper electrode 26. As a result, as shown in FIG. 7C, active hydrogen 63 is generated.
As shown in FIG. 7C, the active hydrogen 63 disperses in the upper electrode 26. As a result, as shown in FIG. 7D, the hydrogen 63 disperses in the capacitor element 35. This means the active hydrogen 63 disperses in the capacitor film 25 through the contact hole 29 and through the contact hole 30. This reduces the capacitor film 25 formed of an insulating metal oxide, and then creates characteristic degradation on the capacitor element 35.
The catalytic reaction generating the active hydrogen 63 on the surface 26A of the upper electrode 26 and a surface 24A of the lower electrode 24 inevitably occurs during the removal step of the resist layer 61 using an O.sub.2 plasma after the etching for forming the contact hole 31 to expose the upper electrode 26 and the lower electrode 24, both formed of platinum, as shown in FIG. 8.
The conventional semiconductor memory device 500 cannot suppress this catalytic reaction. Therefore, the conventional semiconductor memory device 500 has the problem of creating characteristic degradation of the capacitor element 35 due to the reduction reaction of the capacitor film 25 formed of an insulating metal oxide.